A semiconductor integrated circuit which includes a plurality of parallel pairs of MOS transistor rows is known. Each pair includes a row of P-channel MOS transistors and a row of N-channel MOS transistors. In each row, a transistor shares its source/drain regions with its adjacent transistors so that the transistors in that row are connected in series. Applying a cut-off potential to the gate of one transistor in the row can disconnect two transistors adjacent thereto so that the row is divided into two.
An example of such conventional memory arrays formed by integrated circuits comprises memory cells, each including a flip-flop formed by first and second inverters connected in loop, a buffering third inverter connected to the flip-flop, and a read access gate connected to the third inverter. Each inverter is formed by a combination of P-channel and N-channel transistors, P-channel transistors are arranged in rows, and N-channel transistors are also arranged in rows.
Thus, each memory cell uses transistors in a pair of rows of P-channel and N-channel transistors. The first and second inverters are disposed adjacent to each other, and the third inverter is disposed with isolating transistors interposed between the first and second inverters, on one hand, and the third inverter, on the other. The write access gate is disposed adjacent to the first inverter, and the read access gate is disposed adjacent to the third inverter. A number of such memory cells are formed with transistors in each row pair, with isolating transistors interposed between adjacent memory cells.
Conventional memory cells of the described type are intended to receive either of "H" and "L" data applied from the write access gate to write the received data into the flip-flop. However, a problem may arise, when date "H" is written into the flip-flop which has data "L" stored therein. Under such a condition, sometimes the flip-flop will not invert and, therefore, data "H" is not written into it. Inversion of states of flip-flops can be facilitated, if three or more transistors are used to form each of the inverters of the flip-flops. However, even if such provision is made, if the write signal voltage is lower than the desired level, reliable writing cannot be done.
Accordingly, a first object of the the present invention is to provide a memory cell circuit into which data can be written stably a a high speed.
The above-described conventional memory cell array arrangement needs isolating transistors disposed between the second and third inverters of each memory cell and between adjacent memory cells in the memory cell array, such that each memory cell requires a larger number of transistors. The number of transistors which each memory cell uses increases particularly when the inverters forming the flip-flop use three or more transistors in order to facilitate inversion of the flip-flop.
Therefore a second object of the present invention is to arrange the memory cells to require a small number of transistors so that the substrate surface can be utilized efficiently.